1. Field of the Invention
The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a processor dedicated to performing a particular processing sequence.
2. Description of the Related Art
Information processing apparatus available in recent years are finding growing use because of their increasing processing capability. The information processing apparatus are required to carry out more sophisticated processing operation or to process large amounts of data such as still image data and moving image data at higher speeds. According to one known solution, an information processing apparatus has a DSP (Digital Signal Processor) separate from a host processor and dedicated to performing a particular processing sequence such as a still image processing sequence or a moving image processing sequence. A conventional information processing apparatus having such a DSP is illustrated in FIG. 1 of the accompanying drawings. FIG. 1 shows in block form an information processing apparatus disclosed in Japanese laid-open patent publication No. H05-204828.
As shown in FIG. 1, the conventional information processing apparatus has host processor 101, DSP 102, DSP instruction memory 105 for temporarily storing instructions to be supplied to DSP 102, DSP data memory 106 for temporarily storing data to be processed or data processed by DSP 102, host system memory 103 for storing data to be processed and data processed by host processor 101 and DSP 102, and DMA controller 107 for controlling the transmission of data and instructions to and the reception of data and instructions from DSP 102.
Host processor 101 and host system memory 103 are connected to each other by system bus 104, and DSP 102, DSP instruction memory 105, and DSP data memory 106 are connected to each other by DMA bus 108. Host processor 101 and DSP 102 are connected to each other for exchanging data and instructions by DMA controller 107 which provides a link between system bus 104 and DMA bus 108.
In the information processing apparatus shown in FIG. 1, since DSP 102 performs a particular processing sequence, the processing burden on host processor 101 is reduced. In addition, DSP 102 has a shorter processing time than host processor 101 because DSP 102 is dedicated to performing a particular process for which DSP 102 is designed.
If host processor 101 asks DSP 102 to perform a certain process, host processor 101 sends DSP 102 a “data transfer packet request list” including addresses of host system memory 103 where data to be processed are stored, addresses of DSP data memory 106 where the data are to be stored, and information representing the data size. When DSP 102 receives the “data transfer packet request list”, DSP 102 extracts the addresses of host system memory 103, the addresses of DSP data memory 106, and the information representing the data size from the “data transfer packet request list”. Based on the extracted addresses and the data size, DSP 102 activates DMA controller 107 and controls DMA controller 107 to read the data whose size has been indicated from the addresses of host system memory 103 and sends the read data by way of DMA transfer to the addresses of DSP data memory 106. DSP 102 then performs a programmed process on the data transferred to DSP data memory 106 according to instructions stored in DSP instruction memory 105, for example, and stores the processed data back into DSP data memory 106.
When the process is over, DSP 102 activates DMA controller 107, sends the processed data through DMA controller 107 to host system memory 103, and stores the processed data back into host system memory 103, based on another “data transfer packet request list”.
For further improving the processing capability, the above information processing apparatus may additionally have a plurality of subprocessors including microprocessors, DSPs, etc. for performing a plurality of processing sequences parallel to each other. However, the information processing apparatus with the subprocessors is unable to keep the order of input data supplied to the subprocessors and the order of output data received from the subprocessors equal to each other.
For example, a DSP performs a process on each item of input data in the order in which the data are input, and outputs the processed data in the order in which they are processed. In the conventional information processing apparatus with one DSP as shown in FIG. 1, therefore, processed data may be received in the order in which the data are transferred to the DSP, and the host processor can associate the input data and the output data with each other.
If an information processing apparatus has a plurality of DSPs as subprocessors and the DSPs have different processing times that are required to process data, then DSPs having shorter processing times output processed data earlier, so that the order of input data supplied to the DSPs and the order of output data received from the DSPs are different from each other. Accordingly, the information processing apparatus with plural DSPs needs some scheme for managing an association between the input data and the output data in order to recognize which input data have produced processed output data.
If a complex hardware arrangement or increased complex processing is required in order to manage an association between the input data and output data, then it will offset the increase that is achieved in the processing capability of the information processing apparatus by performing a plurality of processes parallel to each other. Therefore, for performing a plurality of processes parallel to each other using subprocessors, it is desirable to construct a system for transferring data to the subprocessors highly efficiently, minimizing information required for management, and eliminating wasteful response wait times due to conflicts between the subprocessors and the CPU.